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19-0791; Rev 2; 6/10
KIT ATION EVALU E AILABL AV
Universal GPS Receiver
General Description Features
o o o o o o o o o o o GPS/GLONASS/Galileo Receivers No External IF SAW or Discrete Filters Required Programmable IF Frequency Fractional-N Synthesizer with Integrated VCO Supports Wide Range of Reference Frequencies Dual-Input Uncommitted LNA for Separate Passive and Active Antenna Inputs 1.4dB Cascade Noise Figure Integrated Crystal Oscillator Integrated Active Antenna Sensor 10mA Supply Current in Low-Power Mode 2.7V to 3.3V Supply Voltage Small, 28-Pin, RoHS-Compliant, Thin QFN LeadFree Package (5mm x 5mm)
MAX2769
The MAX2769 is the industry's first global navigation satellite system (GNSS) receiver covering GPS, GLONASS, and Galileo navigation satellite systems on a single chip. This single-conversion, low-IF GNSS receiver is designed to provide high performance for a wide range of consumer applications, including mobile handsets. Designed on Maxim's advanced, low-power SiGe BiCMOS process technology, the MAX2769 offers the highest performance and integration at a low cost. Incorporated on the chip is the complete receiver chain, including a dual-input LNA and mixer, followed by the image-rejected filter, PGA, VCO, fractional-N frequency synthesizer, crystal oscillator, and a multibit ADC. The total cascaded noise figure of this receiver is as low as 1.4dB. The MAX2769 completely eliminates the need for external IF filters by implementing on-chip monolithic filters and requires only a few external components to form a complete low-cost GPS receiver solution. The MAX2769 is the most flexible receiver on the market. The integrated delta-sigma fractional-N frequency synthesizer allows programming of the IF frequency within a 40Hz accuracy while operating with any reference or crystal frequencies that are available in the host system. The integrated ADC outputs 1 or 2 quantized bits for both I and Q channels, or up to 3 quantized bits for the I channel. Output data is available either at the CMOS logic or at the limited differential logic levels. The MAX2769 is packaged in a compact 5mm x 5mm, 28-pin thin QFN package with an exposed paddle. The part is also available in die form. Contact the factory for further information.
Ordering Information
PART MAX2769ETI+ MAX2769E/W TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* Dice (In Wafer Form)
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed paddle.
Pin Configuration/Block Diagram
VCCADC CLKOUT XTAL 15 14 ADC ADC VCCD Q0 Q1 17 I1 I0 20
21 N.C. 22 VCCIF
19
18
16
Applications
Location-Enabled Mobile Handsets PNDs (Personal Navigation Devices) PMPs (Personal Media Players) PDAs (Personal Digital Assistants) In-Vehicle Navigation Systems Telematics (Asset Tracking, Inventory Management) Recreational/Marine Navigation/Avionics Software GPS Laptops and Ultra-Mobile PCs Digital Still Cameras and Camcorders
23
MAX2769
PLL
13
VCCCP
IDLE 24 LNA2 FILTER 25 90 LNA2
12
CPOUT
VCO
11
VCCVCO
PGM
26
10 3-WIRE INTERFACE
CS
LNA1
0
27
LNA1
9
SCLK
TSENS
28
+ 1 ANTFLAG 2 LNAOUT 3 ANTBIAS 4 VCCRF 5 MIXIN 6 LD 7 SHDN
8
SDATA
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Universal GPS Receiver MAX2769
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.2V Other Pins to GND ..................-0.3V to +(Operating VCC + 0.3V) Maximum RF Input Power ..............................................+15dBm Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derates 27mW/C above +70C)...2500mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (TQFN only, soldering, 10s) ..............+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage Default mode, LNA1 is active (Note 2) Supply Current Default mode, LNA2 is active (Note 2) Idle ModeTM, IDLE = low Shutdown mode, SHDN = low Voltage Drop at ANTBIAS from VCCRF Short-Circuit Protection Current at ANTBIAS Active Antenna Detection Current DIGITAL INPUT AND OUTPUT Digital Input Logic-High Digital Input Logic-Low Measure at the SHDN pin Measure at the SHDN pin 1.5 0.4 V V Sourcing 20mA at ANTBIAS ANTBIAS is shorted to ground To assert logic-high at ANTFLAG CONDITIONS MIN 2.7 15 12 TYP 2.85 18 15 1.5 20 0.2 57 1.1 A V mA mA MAX 3.3 22 19 mA UNITS V
Idle Mode is a trademark of Maxim Integrated Products, Inc.
2 _______________________________________________________________________________________
Universal GPS Receiver
AC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. LNA input is driven from a 50 source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k || 7.5pF on each pin. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER CASCADED RF PERFORMANCE RF Frequency Noise Figure Out-of-Band 3rd-Order Input Intercept Point In-Band Mixer Input Referred 1dB Compression Point Mixer Input Return Loss Image Rejection Spurs at LNA1 Input Maximum Voltage Gain Variable Gain Range FILTER RESPONSE Passband Center Frequency FBW = 00 Passband 3dB Bandwidth Lowpass 3dB Bandwidth Stopband Attenuation LNA LNA1 INPUT Power Gain Noise Figure Input IP3 Output Return Loss Intput Return Loss LNA2 INPUT Power Gain Noise Figure Input IP3 Output Return Loss Input Return Loss (Note 5) 13 1.14 1 19 11 dB dB dBm dB dB (Note 5) 19 0.83 -1.1 10 8 dB dB dBm dB dB FBW = 10 FBW = 01 FBW = 11 3rd-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 5th-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 41 4 2.5 4.2 8 9 30 49.5 MHz dB MHz MHz LO leakage Reference harmonics leakage Measured from the mixer to the baseband analog output 91 55 L1 band LNA1 input active, default mode (Note 3) LNA2 input active, default mode (Note 3) Measured at the mixer input Measured at the mixer input (Note 4) Measured at the mixer input 1575.42 1.4 2.7 10.3 -7 -85 10 25 -101 -103 96 59 103 dBm dBm dB dB dBm dB dB dB MHz CONDITIONS MIN TYP MAX UNITS
MAX2769
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3
Universal GPS Receiver MAX2769
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. LNA input is driven from a 50 source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k || 7.5pF on each pin. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER FREQUENCY SYNTHESIZER LO Frequency Range LO Tuning Gain Reference Input Frequency Main Divider Ratio Reference Divider Ratio Charge-Pump Current ICP = 0 ICP = 1 Sine wave 0.4 /4 x2 8 36 1 0.5 1 0.4V < VTUNE < 2.4V 1550 57 44 32,767 1023 1610 MHz MHz/V MHz -- -- mA CONDITIONS MIN TYP MAX UNITS
TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER Reference Input Level Clock Output Multiply/Divide Range ADC ADC Differential Nonlinearity ADC Integral Nonlinearity AGC enabled, 3-bit output AGC enabled, 3-bit output 0.1 0.1 LSB LSB VP-P --
Note 1: MAX2769 is production tested at TA = +25C. All min/max specifications are guaranteed by design and characterization from -40C to +85C, unless otherwise noted. Default register settings are not production tested or guaranteed. User must program the registers upon power-up. Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically disabled and LNA2 becomes active. PLL is in an integer-N mode with fCOMP = fTCXO / 16 = 1.023MHz and ICP = 0.5mA. The complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz. Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only. Note 3: The LNA output connects to the mixer input without a SAW filter between them. Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm/tone. Passive pole at the mixer output is programmed to be 13MHz. Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm per tone.
4
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Universal GPS Receiver
Typical Operating Characteristics
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. LNA input is driven from a 50 source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k || 7.5pF on each pin. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.)
CASCADED RECEIVER GAIN vs. PGA GAIN CODE
MAX2769 toc01
MAX2769
CASCADED GAIN AND NOISE FIGURE vs. TEMPERATURE
2.0
MAX2769 toc02
LNA1 |S21| AND |S12| vs. FREQUENCY
30 115 |S21|
MAX2769 toc03
120 CASCADED RECEIVER GAIN (dB) TA = -40C 100 TA = +25C 80 TA = +85C 60
120
40
1.5 NOISE FIGURE (dB) 110 NOISE FIGURE 105 100 0.5 95 CASCADED GAIN AGC GAIN 1.0
LNA1 |S21| AND |S12| (dB)
20 10 0 -10 -20 -30 -40 -50 |S12|
40 0 5 10 15 20 25 30 35 40 45 50 55 60 65 PGA GAIN CODE (DECIMAL FORMAT)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
90
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 FREQUENCY (GHz)
LNA1 GAIN AND NOISE FIGURE vs. LNA1 BIAS DIGITAL CODE
1.6 1.4 1.2 NOISE FIGURE (dB) 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LNA BIAS DIGITAL CODE (DECIMAL) 0 10 NOISE FIGURE 5 GAIN 20 NOISE FIGURE (dB) 1.0 0.8 0.6 0.4 0.2 0 -40 LNA1 GAIN (dB)
MAX2769 toc04
LNA1 GAIN AND NOISE FIGURE vs. TEMPERATURE
25 1.4 1.2
MAX2769 toc05
LNA BIAS = 1000
19.6 19.4 19.2 LNA1 GAIN (dB) 19.0 18.8 18.6 18.4
15
NOISE FIGURE
GAIN
18.2 18.0 17.8
-15
10
35
60
85
TEMPERATURE (C)
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5
Universal GPS Receiver MAX2769
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. LNA input is driven from a 50 source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k || 7.5pF on each pin. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.)
LNA1 INPUT 1dB COMPRESSION POINT vs. LNA1 BIAS DIGITAL CODE
MAX2769 toc06
LNA2 |S21| AND |S12| vs. FREQUENCY
MAX2769 toc07
LNA2 GAIN AND NOISE FIGURE vs. TEMPERATURE
2.0 1.8 1.6 NOISE FIGURE (dB) LNA2 GAIN (dB) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 12.4 12.2 -40 -15 10 35 60 85 TEMPERATURE (C) 12.8 NOISE FIGURE GAIN 12.6 13.2 13.0
MAX2769 toc08
LNA1 INPUT 1dB COMPRESSION POINT (dBm)
5.0 2.5 0 -2.5 -5.0 -7.5 -10.0 -12.5 -15.0
30 |S21| 20 LNA2 |S21| AND |S12| (dB) 10 0 -10 -20 -30 -40 -50 |S12|
LNA BIAS = 10
13.6 13.4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LNA BIAS DIGITAL CODE (DECIMAL)
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 FREQUENCY (GHz)
LNA INPUT RETURN LOSS vs. FREQUENCY
MAX2769 toc09
LNA OUTPUT RETURN LOSS vs. FREQUENCY
MAX2769 toc10
MIXER INPUT REFERRED IP1dB vs. OFFSET FREQUENCY
PGA GAIN = 32dB -10 -20 -30 -40 -50 -60 -70 -80 PRF = -100dBm 0 50 100 150 200 250 300 PGA GAIN = 51dB
MAX2769 toc11
0 LNA1 LNA INPUT RETURN LOSS (dB) -10
0 LNA OUTPUT RETURN LOSS (dB)
0 MIXER INPUT REFERRED IP1dB (dB)
-5 LNA1 -10
-20
-30 LNA2 -40
-15 LNA2 -20
-50 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 FREQUENCY (GHz)
-90 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 FREQUENCY (GHz)
OFFSET FREQUENCY (MHz)
6
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Universal GPS Receiver
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. LNA input is driven from a 50 source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k || 7.5pF on each pin. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.)
1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY
0
MAX2769 toc12a MAX2769 toc12b
MAX2769
MIXER INPUT REFERRED NOISE FIGURE vs. PGA GAIN
MIXER INPUT REFERRED NOISE FIGURE (dB)
MAX2769 toc13
16
JAMMER POWER (dBm)
-5
14
12
-10
10
-15
8
-20 800 825 850 875 900 1800 1850 JAMMER FREQUENCY (MHz) 925 950 1900 1950 2000 2050 2100
6 5 15 25 35 45 55 65 PGA GAIN (dB)
3RD-ORDER POLYPHASE FILTER MAGNITUDE RESPONSE vs. BASEBAND FREQUENCY
MAX2769 toc14
5TH-ORDER POLYPHASE FILTER MAGNITUDE RESPONSE vs. BASEBAND FREQUENCY
MAX2769 toc15
MIXER INPUT REFERRED GAIN vs. PGA GAIN CODE
MAX2769 toc16
10 0 MAGNITUDE (dB) -10 -20 -30 -40 -50 -60 1 2 3 4 5 6 7 8 9
10 0 -10 MAGNITUDE (dB) -20 -30 -40 -50 -60 -70
100 MIXER INPUT REFERRED GAIN (dB) TA = -40C 80 TA = +25C 60 TA = +85C 40
20 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 PGA GAIN CODE (DECIMAL FORMAT) BASEBAND FREQUENCY (MHz)
10
BASEBAND FREQUENCY (MHz)
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7
Universal GPS Receiver MAX2769
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC = 2.7V to 3.3V, TA = -40C to +85C, PGM = GND. Registers are set to the default power-up states. LNA input is driven from a 50 source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k || 7.5pF on each pin. Typical values are at VCC = 2.85V and TA = +25C, unless otherwise noted.)
2-BIT ADC TRANSFER CURVE
MAX2769 toc17a
3-BIT ADC TRANSFER CURVE
7 6 CODE (DECIMAL VALUE) 5 4 3 2 1
MAX2769 toc17b
3.5 3.0 CODE (DECIMAL VALUE) 2.5 2.0 1.5 1.0 0.5 0
0 -0.5 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL VOLTAGE (V) DIFFERENTIAL VOLTAGE (V)
DIGITAL OUTPUT CMOS LOGIC
MAX2760 toc18
DIGITAL OUTPUT DIFFERENTIAL LOGIC
MAX2760 toc19
CLK 2V/div CLK 1V/div SIGN DATA 2V/div
SIGN+ 1V/div SIGN1V/div
MAGNITUDE DATA 2V/div 20ns/div 40ns/div
MAX2769 toc20
CRYSTAL OSCILLATOR FREQUENCY (kHz)
8 6 4 2 0 -2 -4 -6 -8 -10 -40 -15 10 35 60
16,368.05
TA = +25C
16,368.00 TA = -40C 16,367.95 TA = +85C
16,367.90
16,367.85 0 4 8 12 16 20 24 28 32 DIGITAL TUNING CODE (DECIMAL)
85
TEMPERATURE (C)
8
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MAX2769 toc21
16,368.10
CRYSTAL OSCILLATOR FREQUENCY VARIATION (ppm)
CRYSTAL OSCILLATOR FREQUENCY vs. DIGITAL TUNING CODE
CRYSTAL OSCILLATOR FREQUENCY VARIATION vs. TEMPERATURE
10
Universal GPS Receiver MAX2769
Typical Application Circuit
REFERENCE INPUT C11 XTAL C6 14 ADC ADC VCCD 15 BASEBAND CLOCK CLKOUT 16 C10 Q0 18 Q1 17 BASEBAND OUTPUT
VCCADC 19
TOP VIEW
I1 21 C8 N.C. 22 VCCIF I0 20
C7
23
MAX2769
PLL
13
VCCCP
C5
IDLE 24 LNA2 FILTER 25 90 LNA2
CPOUT 12 C1 VCO 11 VCCVCO C4 10 3-WIRE INTERFACE CS SERIAL INPUT C2
PGM C0
26
LNA1
0
27
LNA1
9
SCLK
N.C.
28
+ 1 ANTFLAG LNAOUT 2 3 ANTBIAS VCCRF 4 5 MIXIN 6 SHDN LD 7
8
SDATA
C3 ACTIVE ANTENNA BIAS C12
C13
Table 1. Component List
DESIGNATION C0 C1 C2 C3-C8 C10, C11 C12 C13 R1 QUANTITY 1 1 1 6 2 1 1 1 0.47nF AC-coupling capacitor 27pF PLL loop filter capacitor 0.47nF PLL loop filter capacitor 0.1F supply voltage bypass capacitor 10nF AC-coupling capacitor 0.47nF AC-coupling capacitor 0.1nF supply voltage bypass capacitor 20k PLL loop filter resistor DESCRIPTION
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Universal GPS Receiver MAX2769
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -- NAME ANTFLAG LNAOUT ANTBIAS VCCRF MIXIN LD SHDN SDATA SCLK CS VCCVCO CPOUT VCCCP VCCD XTAL CLKOUT Q1 Q0 VCCADC I0 I1 N.C. VCCIF IDLE LNA2 PGM LNA1 N.C. EP FUNCTION Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the ANTBIAS pin. LNA Output. The LNA output is internally matched to 50. Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna. RF Section Supply Voltage. Bypass to GND with 100nF and 100pF capacitors in parallel as close as possible to the pin. Mixer Input. The mixer input is internally matched to 50. Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked. Operation Control Logic Input. A logic-low shuts off the entire device. Data Digital Input of 3-Wire Serial Interface Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising edge of the SCLK. Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high when the loading action is completed. VCO Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin. Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and C (see the Typical Application Circuit). PLL Charge-Pump Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin. Digital Circuitry Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin. XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used. Reference Clock Output Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or 1-bit limited differential logic output or analog differential voltage output. ADC Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin. I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or 1-bit limited differential logic output or analog differential voltage output. No Connection. Leave this pin unconnected. IF Section Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin. Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active, and all other blocks are off. LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50. Logic Input. Connect to GND to use the serial interface. A logic-high allows programming to 8 hardcoded by device states connecting SDATA, CS, and SCLK to supply or ground according to Table 3. LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50 (see the Typical Application Circuit). No connection. Leave this pin open. Exposed Paddle. Ultra-low-inductance connection to ground. Place several vias to the PCB ground plane.
10
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Universal GPS Receiver
Detailed Description
Integrated Active Antenna Sensor
The MAX2769 includes a low-dropout switch to bias an external active antenna. To activate the antenna switch output, set ANTEN in the Configuration 1 register to logic 1. This closes the switch that connects the antenna bias pin to VCCRF to achieve a low 200mV dropout for a 20mA load current. A logic-low in ANTEN disables the antenna bias. The active antenna circuit also features short-circuit protection to prevent the output from being shorted to ground.
16 CLKOUT 10nF BASEBAND CLOCK
MAX2769
MAX2769
15
XTAL 23pF
Low-Noise Amplifier (LNA)
The MAX2769 integrates two low-noise amplifiers. LNA1 is typically used with a passive antenna. This LNA requires an AC-coupling capacitor. In the default mode, the bias current is set to 4mA, the typical noise figure and IIP3 are approximately 0.8dB and -1.1dBm, respectively. LNA1 current can be programmed through ILNA in Configuration 1 register. In the low-current mode of 1mA, the typical noise figure is degraded to 1.2dB and the IIP3 is lowered to -15dBm. LNA2 is typically used with an active antenna. The LNA2 is internally matched to 50 and requires a DC-blocking capacitor. Bits LNAMODE in the Configuration 1 register control the modes of the two LNAs. See Table 6 for the LNA mode settings and current selections.
Figure 1. Schematic of the Crystal Oscillator in the MAX2679 EV Kit
through a control word (GAINREF). The desired magnitude bit density is expressed as a value of GAINREF in a decimal format divided by the counter length of 512. For example, to achieve the magnitude bit density of 33%, which is optimal for a 2-bit converter, program the GAINREF to 170, so that 170 / 512 = 33%.
Baseband Filter
The baseband filter of the receiver can be programmed to be a lowpass filter or a complex bandpass filter. The lowpass filter can be configured as a 3rd-order Butterworth filter for a reduced group delay by setting bit F3OR5 in the Configuration 1 register to be 1 or a 5th-order Butterworth filter for a steeper out-of-band rejection by setting the same bit to be 0. The two-sided 3dB corner bandwidth can be selected to be 2.5MHz, 4.2MHz, 8MHz, or 18MHz (only to be used as a lowpass filter) by programming bits FBW in the Configuration 1 register. When the complex filter is enabled by changing bit FCENX in the Configuration 1 register to 1, the lowpass filter becomes a bandpass filter and the center frequency can be programmed by bits FCEN in the Configuration 1 register.
Mixer
The MAX2769 includes a quadrature mixer to output lowIF or zero IF I and Q signals. The quadrature mixer is internally matched to 50 and requires a low-side LO injection. The output of the LNA and the input of the mixer are brought off-chip to facilitate the use of a SAW filter.
Programmable Gain Amplifier (PGA)
The MAX2769 integrates a baseband programmable gain amplifier that provides 59dB of gain control range. The PGA gain can be programmed through the serial interface by setting bits GAININ in the Configuration 3 register. Set bits 12 and 11 (AGCMODE) in the Configuration 2 register to 10 to control the gain of the PGA directly from the 3-wire interface.
Synthesizer
The MAX2769 integrates a 20-bit sigma-delta fractional-N synthesizer allowing the device to tune to a required VCO frequency with an accuracy of approximately 40Hz. The synthesizer includes a 10-bit reference divider with a divisor range programmable from 1 to 1023, a 15-bit integer portion main divider with a divisor range programmable from 36 to 32767, and also a 20-bit fractional portion main divider. The reference divider is programmable by bits RDIV in the PLL integer division ratio register (see Table 10), and can accommodate reference frequencies from 8MHz to 44MHz. The reference divider needs to be set so the comparison frequency falls between 0.05MHz to 32MHz.
11
Automatic Gain Control (AGC)
The MAX2769 provides a control loop that automatically programs PGA gain to provide the ADC with an input power that optimally fills the converter and establishes a desired magnitude bit density at its output. An algorithm operates by counting the number of magnitude bits over 512 ADC clock cycles and comparing the magnitude bit count to the reference value provided
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Universal GPS Receiver MAX2769
Table 2. Output Data Format
INTEGER VALUE 7 5 3 1 -1 -3 -5 -7 SIGN/MAGNITUDE 1b 0 0 0 0 1 1 1 1 1.5b 01 01 01 00 00 10 10 10 2b 01 01 00 00 10 10 11 11 2.5b 011 001 001 000 000 101 101 111 3b 011 010 001 000 100 101 110 111 1b 1 1 1 1 0 0 0 0 UNSIGNED BINARY 1.5b 10 10 10 11 11 01 01 01 2b 11 11 10 10 01 01 00 00 2.5b 101 100 100 011 011 001 001 000 3b 111 110 101 110 011 010 001 000 TWO'S COMPLEMENT BINARY 1b 0 0 0 0 1 1 1 1 1.5b 01 01 01 00 00 11 11 11 2b 01 01 00 00 11 11 10 10 2.5b 101 100 100 011 011 111 111 110 3b 011 010 001 000 111 110 101 100
The PLL loop filter is the only external block of the synthesizer. A typical PLL filter is a classic C-R-C network at the charge-pump output. The charge-pump output sink and source current is 0.5mA by default, and the LO tuning gain is 57MHz/V. As an example, see the Typical Application Circuit for the recommended loopfilter component values for fCOMP = 1.023MHz and loop bandwidth = 50kHz. The desired integer and fractional divider ratios can be calculated by dividing the LO frequency (f LO ) by fCOMP. fCOMP can be calculated by dividing the TCXO frequency (f TCXO ) by the reference division ratio (RDIV). For example, let the TCXO frequency be 20MHz, RDIV be 1, and the nominal LO frequency be 1575.42MHz. The following method can be used when calculating divider ratios supporting various reference and comparison frequencies:
20MHz Comparison Frequency = TCXO = = 20MHz RDIV 1 LO 1575.42MHz = 78.771 LO Frequency Divider = = M COMP 20MHz
and to center the crystal-oscillator frequency. Take the parasitic loss of interconnect traces on the PCB into account when optimizing the load capacitance. For example, the MAX2769 EV kit utilizes a 16.368MHz crystal that is designed for a 12pF load capacitance. A series capacitor of 23pF is used to center the crystal oscillator frequency, see Figure 1. In addition, the 5-bit serial-interface word, XTALCAP in the PLL Configuration register, can be used to vary the crystal-oscillator frequency electronically. The range of the electronic adjustment depends on how much the chosen crystal frequency can be pulled by the varying capacitor. The frequency of the crystal oscillator used on the MAX2769 EV kit has a range of approximately 200Hz. The MAX2769 provides a reference clock output. The frequency of the clock can be adjusted to crystal-oscillator frequency, a quarter of the oscillator frequency, a half of the oscillator frequency, or twice the oscillator frequency, by programming bits REFDIV in the PLL Configuration register.
ADC
The MAX2769 features an on-chip ADC to digitize the downconverted GPS signal. The maximum sampling rate of the ADC is approximately 50Msps. The sampled output is provided in a 2-bit format (1-bit magnitude and 1-bit sign) by default and also can be configured as a 1-bit, 1.5-bit, or 2-bit in both I and Q channels, or 1-bit, 1.5-bit, 2-bit, 2.5-bit, or 3-bit in the I channel only. The ADC supports the digital outputs in three different formats: the unsigned binary, the sign and magnitude, or the two's complement format by setting bits FORMAT in Configuration register 2. MSB bits are output at I1 or Q1 pins and LSB bits are output at I0 or Q0 pins, for I or Q channel, respectively. In the case of 2.5-bit or 3-bit, output data format is selected in the I channel only, the
Integer Divider = 78(d) = 000 000 0100 1110 (binary) Fractional Divider = 0.771 x 220 = 808452 (decimal) = 1100 0101 0110 0000 0100 In the fractional mode, the synthesizer should not be operated with integer division ratios greater than 251.
Crystal Oscillator
The MAX2769 includes an on-chip crystal oscillator. A parallel mode crystal is required when the crystal oscillator is being used. It is recommended that an AC-coupling capacitor be used in series with the crystal and the XTAL pin to optimize the desired load capacitance
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Universal GPS Receiver MAX2769
011 01 010
001 00 000 -7 -6 -5 -4 -3 -2 -1 1 2 3 4 5 6 7
100
10 101
T=1
110
11 111
Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases
MSB is output at I1, the second bit is at I0, and the LSB is at Q1. Figure 2 illustrates the ADC quantization levels for 2and 3-bit cases and also describes the sign/magnitude data mapping. The variable T = 1 designates the location of the magnitude threshold for the 2-bit case.
divide-by-5 periods. The fractional division ratio is given by: fOUT / fIN = LCOUNT / (4096 - MCOUNT + LCOUNT) where LCOUNT and MCOUNT are the 12-bit counter values programmed through the serial interface.
Fractional Clock Divider
A 12-bit fractional clock divider is located in the clock path prior to the ADC and can be used to generate the ADC clock that is a fraction of the reference input clock. In a fractional divider mode, the instantaneous division ratio alternates between integer division ratios to achieve the required fraction. For example, if the fractional output clock is 4.5 times slower than the input clock, an average division ratio of 4.5 is achieved through an equal series of alternating divide-by-4 and
DSP Interface
GPS data is output from the ADC as the four logic signals (bit0, bit1, bit2, and bit3) that represent sign/magnitude, unsigned binary, or two's complement binary data in the I (bit0 and bit1) and Q (bit2 and bit3) channels. The resolution of the ADC can be set up to 3 bits per channel. For example, the 2-bit I and Q data in sign/magnitude format is mapped as follows: bit0 = ISIGN, bit1 = IMAG, bit2 = QSIGN, and bit3 = QMAG. The data can be serialized in 16-bit segments of bit0, followed by bit1, bit2, and bit3. The number of bits to be serialized is controlled by the bits STRMBITS in the Configuration 3 regis13
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Universal GPS Receiver MAX2769
STRM_EN PIN 21 I ADC Q OUTPUT DRIVER PIN 20 PIN 17 PIN 18 DATA_OUT CLK_SER DATA_SYNC TIME_SYNC STRM_EN STRM_START STRM_STOP STRM_COUNT<2:0> DIEID<1:0> STRM_BITS<1:0> FRM_COUNT<27:0> STAMP_EN DAT_SYNCEN TIME_SYNCEN STRM_RST CLK_ADC CLK_SER STRM_EN
BIT 0 BIT 1 BIT 2 BIT 3
CONTROL SIGNALS FROM 3-WIRE INTERFACE
ADCCLK_SEL
L_CNT<11:0> M_CNT<11:0>
REF/XTAL PIN 15
CLK_IN THROUGH /2 /4 x2
CLK_OUT
FRCLK_SEL
SERCLK_SEL REFDIV<1:0>
Figure 3. DSP Interface Top-Level Connectivity and Control Signals
ter. This selects between bit0; bit0 and bit1; bit0 and bit2; and bit0, bit1, bit2, and bit3 cases. If only bit0 is serialized, the data stream consists of bit0 data only. If a serialization of bit0 and bit1 (or bit2) is selected, the stream data pattern consists of 16 bits of bit0 data followed by 16 bits of bit1 (or bit2) data, which, in turn, is followed by 16 bits of bit0 data, and so on. In this case, the serial clock must be at least twice as fast as the ADC clock. If a 4-bit serialization of bit0, bit1, bit2, and bit3 is chosen, the serial clock must be at least four times faster than the ADC clock. The ADC data is loaded in parallel into four holding registers that correspond to four ADC outputs. Holding registers are 16 bits long and are clocked by the ADC clock.
At the end of the 16-bit ADC cycle, the data is transferred into four shift registers and shifted serially to the output during the next 16-bit ADC cycle. Shift registers are clocked by a serial clock that must be chosen fast enough so that all data is shifted out before the next set of data is loaded from the ADC. An all-zero pattern follows the data after all valid ADC data are streamed to the output. A DATASYNC signal is used to signal the beginning of each valid 16-bit data slice. In addition, there is a TIME_SYNC signal that is output every 128 to 16,384 cycles of the ADC clock.
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Universal GPS Receiver
Preconfigured Device States
When a serial interface is not available, the device can be used in preconfigured states that don't require programming through the serial interface. Connecting the PGM pin to logic-high and SCLK, SDATA, and CS pins to either logic-high or low sets the device in one of the preconfigured states according to Table 3. The serial interface is controlled by three signals: SCLK (serial clock), CS (chip select), and SDATA (serial data). The control of the PLL, AGC, test, and block selection is performed through the serial-interface bus from the baseband controller. A 32-bit word, with the MSB (D27) being sent first, is clocked into a serial shift register when the chip-select signal is asserted low. The timing of the interface signals is shown in Figure 4 and Table 4 along with typical values for setup and hold time requirements.
MAX2769
Serial Interface, Address, and Bit Assignments
A serial interface is used to program the MAX2769 for configuring the different operating modes.
Table 3. Preconfigured Device States
DEVICE STATE DEVICE ELECTRICAL CHARACTERISTICS REFERENCE FREQUENCY (MHz) IF CENTER FREQUENCY (MHz) REFERENCE DIVISION RATIO I AND Q OR I ONLY NUMBER OF I Q BITS IF FILTER ORDER MAIN DIVISION RATIO I AND Q LOGIC LEVEL 3-WIRE CONTROL PINS
DATA
SCLK
0 1 2 3 4 5 6 7
16.368 16.368 16.368 32.736 19.2 18.414 13 16.368
16 16 16 32 96 18 65 16
1536 1536 1536 1536 7857 1539 7857 1536
I I I I I I I I
1 1 2 2 2 2 2 1
Differential Differential CMOS CMOS CMOS CMOS CMOS CMOS
4.092 4.092 4.092 4.092 4.092 1.023* 4.092 4.092
5th 3rd 5th 5th 5th 5th 5th 5th
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
*If the IF center frequency is programmed to 1.023MHz, the filter passband extends from 0.1MHz to 2.6MHz.
CS tCSH tCSS tCSW
SCLK tDS tDH tCH tCL
SDATA
DATA MSB
DATA LSB
ADDR MSB
ADDR LSB
Figure 4. 3-Wire Timing Diagram
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CS 0 1 0 1 0 1 0 1
Universal GPS Receiver MAX2769
Table 4. Serial-Interface Timing Requirements
SYMBOL tCSS tDS tDH tCH tCL tCSH tCSW Data to serial-clock setup time. Data to clock hold time. Serial clock pulse-width high. Clock pulse-width low. Last SCLK rising edge to rising edge of CS. CS high pulse width. PARAMETER Falling edge of CS to rising edge of the first SCLK time. TYP VALUE 10 10 10 25 25 10 1 UNITS ns ns ns ns ns ns clock
Table 5. Default Register Setting
REGISTER NAME CONF1 CONF2 CONF3 PLLCONF DIV FDIV STRM CLK TEST1 TEST2 ADDRESS (A3:A0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 DATA Configures RX and IF sections, bias settings for individual blocks. Configures AGC and output sections. Configures support and test functions for IF filter and AGC. PLL, VCO, and CLK settings. PLL main and reference division ratios, other controls. PLL fractional division ratio, other controls. DSP interface number of frames to stream. Fractional clock-divider values. Reserved for test mode. Reserved for test mode. DEFAULT (D27:D0) A2919A3 0550288 EAFF1DC 9EC0008 0C00080 8000070 8000000 10061B2 1E0F401 14C0402
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Universal GPS Receiver MAX2769
Detailed Register Definitions
Table 6. Configuration 1 (Address: 0000)
DATA BIT CHIPEN IDLE ILNA1 ILNA2 ILO IMIX MIXPOLE LNAMODE MIXEN ANTEN FCEN FBW F3OR5 FCENX FGAIN LOCATION 27 26 25:22 21:20 19:18 17:16 15 14:13 12 11 10:5 4:3 2 1 0 DEFAULT VALUE 1 0 1000 10 10 01 0 00 1 1 001101 00 0 1 1 DESCRIPTION Chip enable. Set 1 to enable the device and 0 to disable the entire device except the serial bus. Idle enable. Set 1 to put the chip in the idle mode and 0 for operating mode. LNA1 current programming. LNA2 current programming. LO buffer current programming. Mixer current programming. Mixer pole selection. Set 1 to program the passive filter pole at mixer output at 36MHz, or set 0 to program the pole at 13MHz. LNA mode selection, D14:D13 = 00: LNA selection gated by the antenna bias circuit, 01: LNA2 is active; 10: LNA1 is active; 11: both LNA1 and LNA2 are off. Mixer enable. Set 1 to enable the mixer and 0 to shut down the mixer. Antenna bias enable. Set 1 to enable the antenna bias and 0 to shut down the antenna bias. IF center frequency programming. Default for fCENTER = 4MHz, BW = 2.5MHz. IF filter center bandwidth selection. D4:D3 = 00: 2.5MHz; 10: 4.2MHz; 01: 8MHz; 11: 18MHz (only used as a lowpass filter). Filter order selection. Set 0 to select the 5th-order Butterworth filter. Set 1 to select the 3rd-order Butterworth filter. Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 0 to select lowpass filter mode. IF filter gain setting. Set 0 to reduce the filter gain by 6dB.
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Universal GPS Receiver MAX2769
Table 7. Configuration 2 (Address: 0001)
DATA BIT IQEN GAINREF -- AGCMODE LOCATION 27 26:15 14:13 12:11 DEFAULT VALUE 0 170d 00 00 DESCRIPTION I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I channel only. AGC gain reference value expressed by the number of MSB counts (magnitude bit density). Reserved. AGC mode control. Set D12:D11 = 00: independent I and Q; 01: I and Q gains are locked to each other; 10: gain is set directly from the serial interface by GAININ; 11: disallowed state. Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X: two's complement binary. Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: 1.5 bits; 010: 2 bits; 011: 2.5 bits, 100: 3 bits. Output driver configuration. Set D5:D4 = 00: CMOS logic, 01: limited differential logic; 1X: analog outputs. LO buffer enable. Set 1 to enable LO buffer or 0 to disable the buffer. Reserved. Identifies a version of the IC.
FORMAT BITS DRVCFG LOEN RESERVED DIEID
10:9 8:6 5:4 3 2 1:0
01 010 00 1 0 00
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Universal GPS Receiver
Table 8. Configuration 3 (Address: 0010)
DATA BIT GAININ FSLOWEN HILOADEN ADCEN DRVEN FOFSTEN FILTEN FHIPEN -- PGAIEN PGAQEN STRMEN LOCATION 27:22 21 20 19 18 17 16 15 14 13 12 11 DEFAULT VALUE 111010 1 0 1 1 1 1 1 1 1 0 0 DESCRIPTION PGA gain value programming from the serial interface in steps of dB per LSB. Low value of the ADC full-scale enable. Set 1 to enable or 0 to disable. Set 1 to enable the output driver to drive high loads. ADC enable. Set 1 to enable ADC or 0 to disable. Output driver enable. Set 1 to enable the driver or 0 to disable. Filter DC offset cancellation circuitry enable. Set 1 to enable the circuitry or 0 to IF filter enable. Set 1 to enable the filter or 0 to disable. Highpass coupling enable. Set 1 to enable the highpass coupling between the filter and PGA, or 0 to disable the coupling. Reserved. I-channel PGA enable. Set 1 to enable PGA in the I channel or 0 to disable. Q-channel PGA enable. Set 1 to enable PGA in the Q channel or 0 to disable. DSP interface for serial streaming of data enable. This bit configures the IC such that the DSP interface is inserted in the signal path. Set 1 to enable the interface or 0 to disable the interface. The positive edge of this command enables data streaming to the output. It also enables clock, data sync, and frame sync outputs. The positive edge of this command disables data streaming to the output. It also disables clock, data sync, and frame sync outputs. Sets the length of the data counter from 128 (000) to 16,394 (111) bits per frame. Number of bits streamed. D5:D4 = 00: I MSB; 01: I MSB, I LSB; 10: I MSB, Q MSB; 11: I MSB, I LSB, Q MSB, Q LSB. The signal enables the insertion of the frame number at the beginning of each frame. If disabled, only the ADC data is streamed to the output. This signal enables the output of the time sync pulses at all times when streaming is enabled by the STRMEN command. Otherwise, the time sync pulses are available only when data streaming is active at the output, for example, in the time intervals bound by the STRMSTART and STRMSTOP commands. This control signal enables the sync pulses at the DATASYNC output. Each pulse is coincident with the beginning of the 16-bit data word that corresponds to a given output bit. This command resets all the counters irrespective of the timing within the stream cycle.
MAX2769
STRMSTART STRMSTOP STRMCOUNT STRMBITS STAMPEN
10 9 8:6 5:4 3
0 0 111 01 1
TIMESYNCEN
2
1
DATSYNCEN
1
0
STRMRST
0
0
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Universal GPS Receiver MAX2769
Table 9. PLL Configuration (Address: 0011)
DATA BIT VCOEN IVCO -- REFOUTEN -- REFDIV LOCATION 27 26 25 24 23 22:21 DEFAULT VALUE 1 0 0 1 1 11 DESCRIPTION VCO enable. Set 1 to enable the VCO or 0 to disable VCO. VCO current-mode selection. Set 1 to program the VCO in the low-current mode or 0 to program in the normal mode. Reserved. Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer. Reserved. Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2; 01: clock frequency = XTAL frequency / 4; 10: clock frequency = XTAL frequency / 2; 11: clock frequency = XTAL. Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: oscillator normal current; 01: buffer normal current; 10: oscillator medium current; 11: oscillator high current. Digital XTAL load cap programming. LD pin output selection. Set D13:D10 = 0000: PLL lock-detect signal. Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA. Set 0 for normal operation or 1 to disable the PLL phase frequency detector. Reserved. Charge-pump test. Set D6:D4 = 000: normal operation; X10: pump up; X01 = pump down; 100 = high impedance; 111: both up and down on. PLL mode control. Set 1 to enable the integer-N PLL or 0 to enable the fractional-N PLL. PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable. Reserved. Reserved.
IXTAL XTALCAP LDMUX ICP PFDEN -- CPTEST INT_PLL PWRSAV -- --
20:19 18:14 13:10 9 8 7 6:4 3 2 1 0
01 10000 0000 0 0 0 000 1 0 0 0
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Universal GPS Receiver MAX2769
Table 10. PLL Integer Division Ratio (Address 0100)
DATA BIT NDIV RDIV -- LOCATION 27:13 12:3 2:0 DEFAULT VALUE 1536d 16d 000 PLL integer division ratio. PLL reference division ratio. Reserved. DESCRIPTION
Table 11. PLL Division Ratio (Address 0101)
DATA BIT FDIV -- LOCATION 27:8 7:0 DEFAULT VALUE 80000h 01110000 PLL fractional divider ratio. Reserved. DESCRIPTION
Table 12. DSP Interface (Address 0110)
DATA BIT LOCATION DEFAULT VALUE DESCRIPTION This word defines the frame number at which to start streaming. This mode is active when streaming mode is enabled by a command STRMEN, but a command STRMSTART is not received. In this case, the frame counter is reset upon the assertion of STRMEN, and it begins its count. When the frame number reaches the value defined by FRMCOUNT, the streaming begins.
FRAMECOUNT
27:0
8000000h
Table 13. Clock Fractional Division Ratio (Address 0111)
DATA BIT L_CNT M_CNT FCLKIN ADCCLK SERCLK MODE LOCATION 27:16 15:4 3 2 1 0 DEFAULT VALUE 256d 1563d 0 0 1 0 Sets the value for the L counter. Sets the value for the M counter. Fractional clock divider. Set 1 to select the ADC clock to come from the fractional clock divider, or 0 to bypass the ADC clock from the fractional clock divider. ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come from the reference divider/multiplier. Serializer clock selection. Set 0 to select the serializer clock output to come from the reference divider/multiplier. DSP interface mode selection. DESCRIPTION
Table 14. Test Mode 1 (Address 1000)
DATA BIT -- LOCATION 27:0 DEFAULT VALUE 1E0F401 DESCRIPTION Reserved.
Table 15. Test Mode 2 (Address 1001)
DATA BIT -- LOCATION 27:0 DEFAULT VALUE 14C0402 DESCRIPTION Reserved.
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Universal GPS Receiver MAX2769
Applications Information
The LNA and mixer inputs require careful consideration in matching to 50 lines. Proper supply bypassing, grounding, and layout are required for reliable performance from any RF circuit. IF center frequency. Either a fractional-N or an integerN mode of the frequency synthesizer can be used depending on the choice of the reference frequency. For Galileo reception, set the IF filter bandwidth to 4.2MHz (FBW = 10) and adjust the IF center frequency through a control word FCEN to the middle of the downconverted signal band. Alternatively, use wideband settings of 8MHz and 18MHz when the receiver is in a zero-IF mode. For GLONASS as well as GPS P-code reception, a zero-IF receiver configuration is used in which the IF filter is used in a lowpass filter mode (FCENX = 1) with a two-sided bandwidth of 18MHz. It is recommended that an active antenna LNA be used in wide-bandwidth applications such that the PGA is operated at lower gain levels for a maximum bandwidth. If a PGA gain is programmed directly from a serial interface, GAININ values between 32 and 38 are recommended. Set the filter pole at the mixer output to 36MHz through MIXPOLE = 1.
Low-Power Operation
The MAX2769 can be operated in a low-power mode by programming the bias current values of individual blocks to their minimum recommended values. The list below summarizes the recommended changes to serial interface registers from their default states to achieve a low-power operation: ILNA1 = 0010 ILNA2 = 00 ILO = 00 IMIX = 00 F3OR5 = 1 ANTEN = 0 BITS = 000 IVCO = 0 REFOUTEN = 0 PLLPWRSAV = 1 In this mode, LNA, mixer, LO, and VCO currents are reduced to their minimum recommended values. The IF filter is configured as a 3rd-order filter. The output data is in a 1-bit CMOS mode in the I channel only. PLL is in an integer-N power-saving mode, which can be used if the main division ratio is divisible by 32. The antenna bias circuitry is disabled. In the low-power mode, the total current consumption reduces to 10mA, while the total cascaded noise figure increases to 3.8dB.
Layout Issues
The MAX2769 EV kit can be used as a starting point for layout. For best performance, take into consideration grounding and routing of RF, baseband, and powersupply PCB proper line. Make connections from vias to the ground plane as short as possible. On the highimpedance ports, keep traces short to minimize shunt capacitance. EV kit Gerber files can be requested at www.maxim-ic.com.
Power-Supply Layout
To minimize coupling between different sections of the IC, a star power-supply routing configuration with a large decoupling capacitor at a central VCC node is recommended. The VCC traces branch out from this node, each going to a separate VCC node in the circuit. Place a bypass capacitor as close as possible to each supply pin This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Do not share the capacitor ground vias with any other branch.
Operation in Wideband Galileo and GLONASS Applications
The use of the wideband receiver options is recommended for Galileo and GLONASS applications. The frequency synthesizer is used to tune LO to a desired frequency, which, in turn, determines the choice of the
Package Information Chip Information
PROCESS: SiGe BiCMOS
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 28 TQFN-EP WAFER 22 PACKAGE CODE T2855+3 WDICE8 DOCUMENT NO. 21-0140 --
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Universal GPS Receiver
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 6/07 1/09 6/10 Initial release Added MAX2769E/W, updated specifications Removed references to temperature sensor function, changed four specifications for SPF, and added soldering temperature DESCRIPTION PAGES CHANGED -- 1, 4, 12, 16, 22 1-4, 8, 9, 10, 14-18, 22
MAX2769
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
23 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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